A real time services are the services where the correctness of the services depending on the timelines and predictability of the services as well as the results of computing. This white paper discusses the domain problems and challenges to the industry to provide quality of real time services. To resolve those problems, this paper proposes the cost effective high throughput real time solution to provide real time system and infrastructure. To examine the real world use cases, Kabira KTS and Sun UltraSPARC T1 processor based Sun Fire T1000 and T2000 are presented. The evaluation test architecture, framework and test cases are illustrated. In addition, this paper steps you through performance management methodology specific to Sun CMT platforms. This paper is targeted to real time system architects, developers, performance engineers and data center service providers to architect, design, implement and deliver compelling real time services.
Background
Real time services require high throughput and low latency for interprocess communication and synchronization, a fast interrupt response time, asynchronous input and output, memory management capabilities, file synchronization, and facilities for satisfying timing requirements etc.
Traditional processor design has long emphasized the performance of a single hardware thread of execution, and focused on providing high levels of instruction-level parallelism (ILP). These increasingly complex processor designs have been driven to very high clock rates (frequencies), often at the cost of increased power consumption and heat production. Unfortunately, the impact of memory latency has meant that even the fastest single-threaded processors spend most of their time stalled, waiting for memory. Complicating this tendency, many of today’s complex commercial workloads are simply unable to take advantage of instruction-level parallelism, instead benefiting from thread-level parallelism (TLP).
Solution Description
Throughput refers to transaction, amount of data transferred via data bus or processing unit within one second, transaction count that the computer system can process in given time. To maximizing the overall throughput of key commercial workloads rather than the speed of a single thread of execution, Chip multi-threading (CMT) processor technology is the key to provide a new thread-rich environment that drives application throughput and processor resource utilization while effectively masking memory access latencies.
Sun UltraSPARC T1 processor is based on CoolThreads(TM) Technology. Combining chip multi-processing and hardware multi-threading with an efficient instruction pipeline, UltraSPARC T1 processor drastically improves computational density and greatly reduce power density.
Providing multiple physical-instruction execution pipelines and several active thread contexts per pipeline.
Effectively masking memory access latencies in multi-thread environment
Providing improved scalability for many multi-thread applications.
“Symmetric Multiprocessing” (SMP) on a chip for developers
Applications scaling well on SMP platforms will do so in UltraSPARC T1 platforms.
A twelve-way associative unified Level 2 (L2) on-chip cache.
Memory latency that is uniform across all cores
Low-latency Double Data Rate 2 (DDR2) memory to reduce stalls.
Improving throughput while using less power and dissipating less heat than conventional CMP platforms.
With CoolThreads, each CPU core can run up to four threads simultaneously
Scaling well for Multi-threaded applications, Multi-process applications and Multi-instance applications
Sun servers with UltraSPARC T1 processors can be configured with four, six, or eight processor cores. Each core employs a 64-bit execution pipeline with four logical processors capable of processing four active execution contexts referred to as threads. This means that the thirty two logical processors in an eight-core processor can process up to thirty two active execution contexts. In addition, UltraSPARC T1 processor, combined with the Solaris 10 Operating System, have provided the foundation for real time computing hosted within a power and space-efficient environment. Furthermore, Solaris container and resource management This allows real time applications to take advantage of the latest technologies while at the same time reducing power, HVAC and space demands.
Solaris Container consists of a group of technologies that work together to efficiently manage system resources, virtualize the environment, and provide a complete, isolated, and secure runtime environment for applications. Solaris containers include two important technologies: Solaris Zones partitioning technology and resource management tools. Solaris Zones enable an administrator to create separate environments for applications on a single system, while the resource management framework allows for the allocation, management, and accounting of system resources such as CPU and memory.
Solaris Zones is a unique partitioning technology used to create an isolated and secure environment for running applications. Zones provides isolation to enhance security and reliability.
Resource Management enables system resources such as CPU resources to be dedicated to specific applications. Resource pools provide the capability to separate workloads so that consumption of CPU resources do not overlap, and also provide a persistent configuration mechanism for processor sets and scheduling class assignment.
Kabira Transaction Switch achieves mainframe level performance, supporting tens of thousands of Transactions Per Second (TPS) on a scalable, continuously available system. The KTS massively parallel threading architecture makes maximum use of the thirty two virtual threads in the UltraSPARC T1 processor. It uses full-featured, Solaris ten on 64-bit SPARC servers rather than using expensive proprietary equipment. When demand increases, the system can scale up linearly with the addition of another blade, or scale out with the addition of another chassis. Kabira leverages this technology to provide eight times the performance of the traditional CMP based platform per socket.
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